Fast growth of the pervasive computing and handheld/communication industry has generated exploding demand for high capacity nonvolatile solid-state data storage devices. Current technology like flash memory has several drawbacks such as slow access speed, limited endurance, and the integration difficulty. Flash memory (NAND or NOR) also faces significant scaling problems.
Resistive sense memories are promising candidates for future nonvolatile and universal memory by storing data bits as either a high or low resistance state. One such memory, MRAM, features non-volatility, fast writing/reading speed, almost unlimited programming endurance and zero standby power. The basic component of MRAM is a magnetic tunneling junction (MTJ). MRAM switches the MTJ resistance by using a current induced magnetic field to switch the magnetization of MTJ. As the MTJ size shrinks, the switching magnetic field amplitude increases and the switching variation becomes more severe. Resistive RAM (RRAM) is another resistive sense memory that has a variable resistance layer that can switch between a high resistance state and a low resistance state (for example by the presence or absence of a conductive filament) by applicant of a current or voltage.
However, many yield-limiting factors must be overcome before resistive sense memory enters the production stage. One challenge is the large resistance variation among the high resistance states and the low resistance states found in a resistive sense memory array. In spin-torque transfer RAM (STRAM), this is exponentially dependent on the thickness of an oxide barrier. The resistance variation in an MRAM, RRAM or STRAM array can be so large that the distributions of the resistance of a reference cell and that of a sensed cell may overlap. In such a situation, a sensing error may occur.